Understanding I2C - Part 2

I2C is a powerful serial communication used in data intensive applications. It replaces a complex parallel interface with a straight forward two-wire interface. Being a Master-Slave interface, each salve in I2C is addressable by a unique address. So, for a 7-bit address from master there can be 2^7 slaves on the line.  The addresses ranging from 0 to 127. The maximum slave count is sometimes limited by the capacitance over the bus. Designers need to keep in mind that for a capacitance of less than 200pf, pull-up is used and capacitance over 200pf requires a current source. The maximum capacitance over I2C as per the standard is 400pf.

How a START/STOP bit differs from other data bits transmission and how come slave differentiates between data and START/STOP bits?

During an I2C data transfer, when the CLK is HIGH, no transition must occur on SDA line. If such transition happens, then it is an indication of either a START/STOP condition.

1.       START condition is indicated by a HIGH to LOW transition when SCK is HIGH.

2.       STOP condition is indicated by a LOW to HIGH transition when SCK is HIGH.

UFm mode:

In Ultra-Fast mode, which can operate at a speed of up to 5Mbps, only unidirectional transfer is possible. There is no ACK from slave as in normal modes. It is a push-pull bus. PCx966x family (I2C bus controller) from NXP supports this ultra high speed I2C transfer.

Applications of I2C:

1.       LED controller/driver

2.       Touch interfaces for display

3.       GPIO Expanders

4.       Memory (EEPROM)

5.       RTC

6.       Gaming industry

7.       Sensors

8.       ADC/DAC

9.       Multiplexer/Switches

10.   Communication modules (BT, Wi-Fi, NFC, .. )

11.   Other control, portable and consumable applications

Advantages of I2C interface:

1.       Simple 2-wire serial interface

2.       Easily programmable

3.       I2C compared to other parallel interfaces reduces the PCB footprint and results in lower system costs.

What if you don’t have a I2C interface on your device?

An I2C bus controller can be used, to convert any of the parallel interfaces to I2C. MAX166x and PCx966x are some of the examples.

How do you simulate I2C data?

If you are working with a microcontroller, the debugging tools provided by that vendor help to trace the I2C data in registers. But if you have a standalone slave device evaluation board without any master and wanted to debug, TOTAL PAHSE provides some debugging tools which helps to simulate your I2C interface. Aardvark I2C/SPI Host Adapter from TOTAL PHASE acts as master and can pump in data to slave. Beagle I2C/SPI Protocol Analyzer helps to analyze the data transitions between them.

Understanding I2C - Part 1

I2C is a serial communication protocol. I2C uses SDA, SCL lines for communication. I2C was initially developed by Philips and is a famous protocol in embedded systems. Whether it may be microcontroller, processor, SoC or an FPGA, I2C interface is a must. I2C uses a 7-bit addressing scheme; also it uses 10-bit address. The data is transferred in bytes over SDA.

I2C uses a Master-Slave configuration with single master and multiple slaves. Also, there can be multiple masters over a link. At any time, only master can initiate a transfer and slave can only respond.  As I2C uses a 7-bit addressing scheme there can be 128 slaves connected over a I2C interface. As I2C transfers can take place only byte at a time, when master transfers a address an 8^th bit will be included which tells the slave whether it is a read or write cycle. A 8^th bit of ‘0’ indicates master writing to slave and ‘1’ indicates master reading from slave.

Depending on speed, three modes are defined in I2C communications:

Low speed mode – 10KHz

Standard mode – 100KHz

Fast Mode – 400KHz

High Speed Mode – 3.4MHz

Ultra Speed Mode – 5MHz (USDA, USCL)

The genuine doubt in the mind of embedded programmer comes in the case of data transfer to slave. For example, if a master wants to transmit 0x79 to slave, the master starts off the transmission from MSB of the byte. So, for 0x79 (01111001) , master transmits ‘0’, ‘1’, ‘1’, ‘1’, ‘1’, ‘0’… in sequence. But during data transfer there will be an extra bit from slave end indicating the status of data transfer, we call it ACK. If ACK from slave is ‘0’, it indicates that data is transferred successfully and ready to accept more. If ACK is ‘1’, data is transferred successfully and no more data to be transferred.

Why do I2C lines require pull-ups?

SDA, SCL are open drain drivers. So, master can drive low but to drive high an external pull-up is required on both SCL and SDA lines.

What is an open drain driver?

This open drain drivers discussion leads to a question of what is open drain driver, why can’t it drive high on it’s own. Going into the details, the I/O buffers on the master can be either open drain or push-pull. In a push-pull configuration, there will be two transistors where one drives the output low and the the other drives high. In a push-pull configuration, the lower transistor drives the output low and the upper transistor drives the output high. In an open drain configuration, there will be only one transistor which can drive the output low and when output must be high it can’t drive on it’s own and needs an external resistor. In TTL world, we call the same open driver as open collector.

What is clock stretching and arbitration in I2C?

Consider, a case in which two controllers are communicating with each other over a I2C line. When a master among it initiates a transfer, there might be case in which the other controller might be busy and it sees initiation from master and holds the SCL low until it finishes off it’s routines. This case of holding the SCL low is called clock stretching. During this time of SCL low, no communication can take place over I2C lines. Arbitration is another case in which SDA is held low.

How to choose a pull-up value for I2C lines?

Choosing I2C pull-ups is a challenge for any designer. Mostly, we go by the recommendations of the manufactures. For low frequency applications in the case of microcontrollers, we can by these recommendations. But in the case of high frequency applications, pull-ups need to be chosen after some study. The pull-up value depends on,

1.    Capacitance of the line.

2.    Length of the line

3.    Speed of transfer.

As the number of slaves over I2C line increases, the capacitance also increases. This capacitance includes capacitance at master, slave end and parasitic capacitance. As capacitance increases, time constant (RC) also increases. This increases the rise time and hence, speed reduces. This can be clearly seen when we probe the I2C lines. The signal tends to rise exponentially. This is not affordable and we have to bring back the square signal. For this as number of slaves increases, we tend to reduce the pull-up resistor value over the line. But there is a disadvantage in reducing pull-up because it causes more current to flow and hence unnecessary leakage and more power dissipation which is not acceptable for low power and battery powered applications. In such cases, only simulations will help to come to a correct solution before freezing off the design.

In case where I2C need to driven over a long distance, the parasitic capacitance will be high and hence we use lower pull-up values. Also, as the speed increases in the case of high speed and ultra high speed mode of I2C, the time constant must be low and hence we tend to use lower pull-up values.

The smallest value of I2C pull-up can be calculated using the formula,

              R(pull-up) = [V(pull-up) – (level over I2C lines)]/current from pull-up

The largest value depends on capacitance and speed of bus and can be calculated using,

              R(pull-up) = [1/Fmax]/Cbus

Cbus = Cmaster + Cslave + Cparasitic