Porting RTOS on LPC2148 - Step 2 (download eclipse)

Eclipse IDE is used by many users worldwide and it is freely available for download. You may use Eclipse integrated with cross compiler tools. Other than Eclipse there are some other tools which we will see in coming articles.

Step 1:

The first step to installing Eclipse is to check if your system has a java runtime (JRE) installed or not.  Eclipse is basically written in Java and requires a JRE to execute.  To check if JRE is installed or not, type the following command in the command prompt (start->run->Type cmd and press enter):

Java –version

The following response must be seen:

If you don’t see a version, download JRE from the following link:

http://www.oracle.com/technetwork/java/javase/downloads/index.html

Step 2:

The next step is to download eclipse.

Download eclipse from the following link:

http://www.eclipse.org/downloads/

Use “Eclipse IDE for C/C++ Developers” as most of our applications will be written in C/C++. An important point here is that, this setup comes up with plugins for C/C++ program development. Plug-ins are nothing but compiler kind of support for executing C/C++ programs. Once the eclipse is downloaded you can install the desired plug-ins also. Note that Eclipse doesn’t have a setup procedure.  Download the eclipse and run the .exe to start working.

Learning PCI

PCI also known as conventional PCI these days is short form for peripheral component interconnect. Basically, PCI is a backplane interconnect bus. PCI is used to connect external hardware to computer local bus.

Brief history:

Before PCI, buses like ISA, EISA and a standard proposed by VESA were used. ISA supported 16-bit bus and operated at 4.77MHz. EISA supported 32-bit bus and operated at 8MHz. The VESA bus was 32-bit and was a direct connection to CPU. It operated at 25MHz. the problem was that it was directly connected to CPU and if more than one device was connected, it used to overload the CPU. Considering all these scenarios, Intel brought PCI into picture which was initially connected to front side bus through a bridge.

PCI is a 32/64-bit bus which is used to connect network card, modems, USB, serial, TV tuner cards, modems to processor. It has a 33MHz and 66MHz variant speeds. The next version of PCI, PCI-X operates at 133MHz. PCI bus extends from main processor to PCI connector which is also called PCI slot. Then the expansion cards (network, sound, etc) are connected to these slots. A device can also be placed on the main board and connected via PCI bus without the need for slots. In such a case, we call it a planar device. PCI bridges are used to connect two PCI buses.

PCI has a variant of +3.3V, +5V cards. The type is decided by the slot on the PCI cards. The notch distance from the back plate determines supply variants. A +3.3V card has notch at a distance of 56.21mm from the back plate. a +5V version card has notch at a distance of 104.47 from the back plate. there are universal cards which have +3.3V as well as +5V support and they have two notches.

PCI uses reflected wave switching technique for transmission. This technique can use a unmatched line for signal transmission. so, due to PCB constraints and signal mismatch, the leading edge at the receiver may have a low level and gets reflected. the reflected signal adds up to the forward signal and this level must be enough for signal detection at the receiver. This helps to have low power consumption, low cost. but only problem is that frequency of transmission will be less as transmitter has to synch up and stop transmission until round trip delay of first bit of data. The opposite of reflected wave switching is incident wave switching which is used in VME bus. This requires stringent matching mechanism as the signal must be received in the first trot without any reflection. This eats up some power.

PCI pin out:

Hardware design considerations of PCI:

• A PCI device connected to slot should not have capacitance of mare than 10pF, else it may cause timing issues
• The maximum routing length for clock is 2.5"
• PRSNT1#, PRSNT2# pins must have pull-up on the main board. These help in detecting the PCI device.
• The routing of INTA# till INTD# to PCI slots is not parallel. they are rotated for each slot. 
• The status of PRSNT1#, PRSNT2# determines power (25W, 15W, 7.5W)
• The routinglength of 32-bit bus is restricted to 1.5" and routing length of 64-bit is restricted to 2"
• A maximum of 10 loads can be connected on a 33MHz PCI bus. Motherboard is treated as one load. A PCI card is treated as two loads. So, a maximum of 4 PCI slots can be present on the PCI bus.
• For a 66MHz operated bus, the load size will be half and with above consideration only two PCI slots can be present.
• For an on-board PCI devices, maximum load is two.
• To enable 66MHz operation, M66EN must be pulled high.

Some important points about PCI:

• PCI in little-endian
• 66MHz devices use only 3.3V
• PCI latency timers work at PCI clock rate. PCI device holds the bus until the counter internally reaches zero. then it releases the bus and any PCI device waiting for the bus can take control in this time.
• When a PCI device is inserted into PCI-X slot, it's speed is limited to that of PCI only. 
• Mostly available devices in market are 5V
• PCI best suites for Wi-Fi applications when compared to USB.
• The PCI frequency can vary from 0 to 33MHz. the actual frequency is 33.333MHz
• When a reset signal is issued, all the PCI signals are tristated.
• The start/stop of transaction in PCI is indicated by FRAME#
• IRDY# is asserted by device to convey that it is ready to transmit/receive data
• PCI specification specifies the timing, electrical, mechanical, protocol requirements of PCI bus.
• Initiator, Agent, Target are the terminologies used to describe PCI devices. Initiator is the master which holds the bus and initiates transaction. Target is the slave and is the target of initiator for data transfer. Either an initiator or target connected to PCI bus is called an agent.

Mini-PCI:

Mini-PCI is a computer bus standard mainly for laptops where as PCI is used for desktops. This is because it is not feasible to have that big slots on a lappy. It is again a 32-bit interface with 33MHz operation switching at 3.3V. This Mini-PCI is power limited and maximum power supported is 2W. there are even options for driving low power modes using pins like CLKRUN# which disables clock. Wi-Fi, BT, Fast Ethernet, modems and other devices use this mini-PCI.  Like PCI, this also supports bus mastering and DMA access. there are 3 form factor cards supported on PCI namely Type I, Type II and Type III. Type I and Type II standard defines 100-pin stacking connector. Type III defines a 124-pin edge connector.

How does interrupts work in PCI?

There are 4 interrupt lines (INTA#, INTB#, INTC#, INTD#) in PCI. These lines are available to all the PCI devices connected to a system. Based on these interrupt lines, the interrupt request is processed by the system BIOS. If two card slots are present, the INTA# position on slot is taken by INTB# on second slot,In this way, the interrupt pins are rotated in the PCI slots. the interrupt service mechanism is little bit complex and may lead to leading edge issues if more than one PCI device tries to drive the interrupt signal. To avoid this problem, Message signaled interrupts are used in PCIe, where device writes to memory to indicate that it is ready to communicate.

Let us assume, a PCI card is plugged in, what are the initial sequence of events that are going to happen?

The device gets the master access to the PCI bus. The presence of PCI bus is determined by the hardware signals. The BIOS is going to read the configuration data of the device plugged in and is stored in configuration space of the memory. This determines the type of card and other characteristics of the card. This further read by operating system determines the memory address space and I/O address space to be assigned. Generally, the address space is in GB and configuration space is 256B.

Antenna Polarization

For any wireless transmission, whether it be mobile, satellite, radio antenna is a must. Choosing desired antenna for particular application needs some study. An antenna can be described as a transducer which converts electrical energy into electromagnetic energy and radiates in the air and viceversa. Electromagnetic signal requires no introduction which is described as combination of electric and magnetic fields oscillating perpendicular to each other and orthogonal to the propagation of wave. It is the electric field component component that is important for us in deciding the antenna type. One way of classifying the antennas is by knowing the type of orientation of E-plane. Types are,

• Linear polarization
• Vertical Polarization
• Horizontal Polarization
• Circular Polarization
• Right hand circularly polarized
• Left hand circularly polarized
• Elliptical polarization 

Linear Polarization: The direction of radiation is in the direction of propagation. In other terms, it is in plane with the direction of propagation.

Circular Polarization: The plane of polarization rotates in a circle. For a time period of one wave, the plane rotates one cycle.

Vertical Polarization:

• The electric filed is perpendicular to the surface of earth
• In case of broadcasting requirements, we use this type of polarized antennas.
• Mobile antennas use vertical polarization
• Other applications include AM broadcast, Whip antennas on all automobiles
• Man made RF noise also is vertically polarized which may cause interference to actual signal of transmission

Horizontal Polarization:

• The electric field is in plane (parallel) with earth's surface.
• Local TV transmissions use this type of polarization
• Generally for less distance, when user feels other noise may interfere with their transmission, they use horizontal polarization

Circular Polarization:

• If the rotation of field is clockwise when looking at the direction of propagation, then it is Right hand circular propagation
• If the rotation of field is counter clock wise when looking at the direction of propagation, then it is called left hand circular polarization.
• This type of antennas are preferred when change in environment conditions should not effect the polarization, satellite communications is one example.
• This polarization is little difficult to generate and is costly.
• Helical antennas, Yagi antennas are also used.
• Patch antennas used for satellite communications generate circular polarization

Elliptical polarization:

• When electric field rotates through all angles in circular polarization, the distance between maximum and minimum peaks is represented by a term called Axial ratio or Ellipticity.
• If Axial ratio is 0 dB, then it is circular polarization
• If axial ratio is >0 dB, then it is elliptical polarization

Other considerations:

• The transmission and reception must have antennas with same type of polarization to get maximum signal reception. Any variations from this may cause signal drop in reception in dB.
• When more than one antenna need to be placed on top of buildings, care to be taken that they should be placed at a distance from each other, so that both doesn't interfere.
• The surroundings also have a effect on transmission. whether it be buildings, hilly areas, the signal strength gets reduced by some amount described by terminology fading. Fading can be short term or long term. For a receiver at a short distance, short term fading is due to multiple reflections from buildings and other obstacles. for a receiver at longer distances, long term fading is due to hilly terains, buildings.
• To enhance reception, engineers employ more than one antenna, which is described by the term diversity reception. combining two outputs and determining a strongest signal is always cumbersome. Even the placement of antennas at a distance causes maintenance costs to increase.

Understanding eye diagram

With the recent trends of increase in complexity of designs, accelerated data rates going up to Gbps and reduced time to market, the designers must have a tool in hand which can predict the problems and report before production. Eye diagram is one such tool which analyzes the quality of high speed signal over a channel. It may be any interface standard, any data rate, it has to comply with the certification standard before releasing to market. Eye diagram comes handy in these cases. 

Eye diagram can be thought of as a amplitude vs time graph over a oscilloscope formed by continuously sampling a high speed signal. Using this user can analyze,

• Transmission line effects
• Termination requirements and effects
• Any impedance mismatch over the line
• Routing problems on a PCB
• Grounding requirements
• Jitter of the signal
• Any crosstalk, inter symbol interference effects
• Signal-to-Noise ratio of a channel
• Overshoot and Undershoot 

The below diagram shows a noisy eye diagram visualized over a oscilloscope:

Few points to remember while using a scope for measuring eye diagram:

• Scope used must have sufficient bandwidth
• Probes with low capacitance
• Scope calibration before measurement
• Keep a check on the probes, oscilloscope vendor may suggest a specific probes for measurement
• To do the eye diagram, user has to transmit data pattern specific to the interface being tested
• Oscilloscope vendors like Agilent, Tektronix provide different applications for interface wise eye diagram measurements
• For eye diagram analysis of a specific interface, user has to transmit data at a rate specific to that interface for unbiased analysis

Eye diagram measurements:

One level:Mean value of high level measured over a channel

Zero Level:Mean value of zero level measured over a channel

Eye Amplitude: Difference between high and low level in the eye diagram. It should not exceed interface specific standards.

Eye height: Measure of eye vertical opening. Lower the height, higher the noise over the channel. So, an eye must never get closed, which indicates noisy channel.

Eye width:Mean of crossing points of sampled digital signals.

Bit Period: This indicates horizontal opening and indicates the data rate in the channel.

Rise Time:Mean transition time in the upward direction

Fall time:Mean transition time in the downward direction

Jitter: Measured in picoseconds, this indicates deviation from the actual bit event.

Compliance mask overlay:

For a specific interface, a standard will be defined and the signal timing and other parameters have to comply to that standards. Compliance mask is like a ideal situation as per the interface standard.The time and amplitude limits as per the standards need to be maintained. By seeing the above figure, you can see a keep out area for eye and then maximum and minimum amplitude requirements. If signal either comes into keepout area or crosses the maximum and minimum limits, then that interface is not compliant as per interface standard.

So, regarding eye diagram we have to keep in mind that it is indicator of system performance. 

Porting RTOS on LPC2148 - Step 1

RTOS porting is of interest for many engineers. We are trying to port RTOS onto LPC2148 using resources available over internet. Before proceeding with the RTOS porting let us list the specifications of LPC2148 relevant to porting:

•          16-bit/32-bit ARM7TDMI-S CPU
•          512kB Flash
•          40kB SRAM
•          Max. Frequency – 60MHz

Can we port Linux based RTOS/Linux on LPC2148?

Linux porting requires MMU on processor. Also, the RAM/ROM requirements of processor are high. LPC2148 doesn’t have MMU. Also, the memory is less on LPC2148. It doesn’t have a direct addressing capability for an external memory (external memory bus). Even the extendable memory like SD card is used only for data storage and not for programming. So, clear that Linux can’t be ported on LPC2148. Expanding this none of the ARM7 can have Linux ported because of above disadvantages. From ARM9 onwards, we can port Linux.

What are some of the RTOS available for porting?

Free or Open source RTOS:

• ·         FreeRTOS
• ·         uCLinux
• ·         eCOS

Closed or Propeitary RTOS:

• ·         VxWorks
• ·         ThreadX
• ·         uC/OS2
• ·         QNX
• ·         Windows CE
• ·         Symbian
• ·         RT Linux

GNU WinARM Tool Chainis used by many people around the world for RTOS compilation and porting.

How a no-voice can understand RTOS?

RTOS is a real-time operating system in which tasks are handled efficiently. Tasks are nothing but simple sub-routines. The processing of such tasks is done as per the pre-defined time constraints. An algorithm named scheduling efficiently handles the tasks.

Some of the terminologies in RTOS:

Non-Preemptive multitasking: It is a scheduling algorithm in RTOS where each of the tasks cooperates with each other to share the processing. Other task Priorities are given respect by the running task. High priority task can interrupt the running task and go to Ready-to-Run state. So, a high priority ISR interrupts the low priority task and once the ISR is executed, the low priority task is executed again. The main disadvantage with this algorithm is that high priority task has to wait. This generally is not used in real time systems.

Preemptive multitasking: It is a scheduling algorithm in RTOS where high priority task is always given priority. Until high priority task releases the CPU, low priority task will not be executed. The exact execution time of high priority task can be determined, hence, kernel using this type of tasking is said to be deterministic.

Semaphore: Consider two tasks competing for a usage of common source. Let us say, they have to output data over same UART or something, in that case someone has to synchronize the resource and allocate it to task. This is said to be resource synchronization and is done by semaphore. There is another case where we read from a UART and write it to memory and we read the same from memory to do some other operation. In this case, the task that is reading must be quick enough to be launched after write task is done. This is what we call task synchronization and also is done by semaphore. Semaphores are two types namely, binary semaphore and counting semaphore. Binary semaphore is used in case of resource synchronization. If two tasks have to share a memory, then in that case we use a counting semaphore. 

Intel Processors - 1

Browse for a list of Intel processors over internet and i bet you will be confused forever!!!! But if you have clear idea of your application and little knowledge of fabs, micro-architecture and cores it isn't that easy to list down.Go to the Intel website and you can get a list of processors under individual tabs desktop, mobile and servers.

Processor used for Mobiles:

• Intel Atom Processors for Tablets and Samrtphones
• Intel Celeron mobile Processor
• Intel Pentium Mobile Processor
• Intel core i3 processor
• Intel core i5 processor
• Intel core i7 processor
• Intel core i7 Extreme processor

Processor used for Desktops:

• Intel Atom Processors
• Intel Celeron Desktop Processors
• Intel Pentium Desktop Processors
• Intel core i3 processor
• Intel core i5 processor
• Intel core i7 processor
• Intel core i7 Extreme processor

Processor used for Servers:

• Intel Atom Processors for server
• Intel Itanium Processors
• Intel Xeon processor E3 family
• Intel Xeon processor 5000 family
• Intel Xeon processor E5 family
• Intel Xeon processor E7 family

The choice of part number can be selected from the following link:

http://www.intel.com/content/www/us/en/processor-comparison/compare-intel-processors.html?select=server

The above list of items are classified based on the following criteria:

• Micro-architecture type
• Fabrication process
• Cores 
• Clocking and other factors
• Power dissipation

Will describe the above criteria in the coming articles

High Speed Signals - Clock

Clock is one of the important signal in a modern day electronics systems. A clock is ideally a square wave. but in real time, due to lot of constraints it is never a square wave, especially at higher frequencies. When we see the frequency plot of this square wave (not exactly a square), we can see different frequencies of varying amplitude. For a low frequency signal, where the rise time is comparatively high, the harmonic amplitude is less and it is viceversa.

Consider a mobile/tablet PCB where you will be having clocks of different frequencies. An I2C may be operating up to 1MHz, SPI around 50MHz range, a DDR operating on a very high frequency, can be up to 666MHz, eMMC operating upto 54MHz and so on. You can see that the frequency of clock is varying as per the interface. So, the design guidelines for each interface varies. We can use an internal PLL in processor for this clocks generation or a external clock distribution devices. Whatever, the clock may get effected by the following problems:

1. Attenuation because of PCB traces
2. Pulse edge distortion
3. Jitter because of impedance mismatch and ringing (undershoot/overshoot)
4. Skew and phase difference
5. Cross Talk
6. EMI

A board Designer must take following precautions to avoid above conditions:

1. Use high swing clock signals
2. Chose proper termination technique to achieve impedance matching and hence eliminate reflections (power dissipation also to be considered)

Also, during layout, following guidelines need to be taken:

1. Place the clock source as close as possible to the device. to say it the other way, use short PCB traces.
2. Avoid using vias for clock. Vias cause impedance mismatch and hence reflections.
3. If the clock is routed on outer layer, take care that it has a reference plane next to it.
4. Route the signal in the inner layers to avoid EMI. The inner layer must be sandwiched by reference planes.
5. Avoid routing clock on different signal layers.
6. Keep the traces as straight as possible. In case of any bend required, do not use right angle bends. Use either 45 degree or arcs.
7. For a differential clock, the distance between P/N must be thrice the height of dielectric. this space must be maintained over the entire routing length.
8. Length matching must be there between P/N, else it results in skew and phase difference.
9. If same clock need to be used for more than one device, avoid using stubs. Instead prefer, daisy chaining or star routing (T topology). The devices to which clock is routed may not be at equal distance from clock source. In this case, use a serpentine routing to match the length.
10. To avoid crosstalk, the distance between two differential pairs must be twice the distance between P&N of individual pair.

More to follow in next article....