Universal Flash Storage (UFS2.0)

Are you buying a mobile or tablet? One of the major specifications that you look at is the storage. The need for memory in embedded products is vital. So, memory is a must in embedded products. We always here of eMMC card that is used in these systems. The memory that we are talking about here is NAND type and this is the type of memory that is used for storage as it is the cheapest memories available. The newest memory interface that the latest processors have to connect memory interfaces is UFS.

UFS is a universal flash storage interface in processors for connecting external memory. UFS is a next generation JEDEC flash memory standard. UFS is a successor to eMMC standard that is commonly used. The removal memory in the embedded systems are interfaces using this interface. The previous eMMC standard uses parallel interface where as the UFS uses serial differential interface for connectivity. The serial differential interface is basically a LVDS signalling method used. On most of the latest mobile processors, you find the UFS interface. The UFS is basically a full-duplex interface. As the interface is full-duplex, this will have separate lines for read and write making it the fastest interface.With UFS we can say that the speed/performance of SSD is combined with storage capacity of eMMC. The speed of UFS based memories can be up to 1200MBps.So, we can achieve the same speed with UFS as well.

The present version of UFS is 2.0. 

Why is UFS preferred?

1. The sequential read/write speeds are high (Faster response times)

2. Lower power consumption.

3. Higher storage bandwidth (Memory density)

4. Lesser space required on PCB for routing

5. Bi-directional transfer

6. The commands are queued which helps for parallel processing

7. Lower latency than eMMC interface

The latest Snapdragon 820 processors have the UFS2.0 interface.

High speed Designs - Part 2

Eye Diagram in communications field is one of the indicator of channel performance. The quality of the signal and in turn channel can be explained by the eye diagram. the eye diagram is a source to analyze the high speed designs. An eye diagram is formed by overlaying of number of bits that are transmitted across the channel. An eye diagram is a pattern that is formed in an oscilloscope which resembles the shape of an eye. If you have validated or performed any certification of high speed interfaces like PCIe, USB, etc., then you know well that eye diagram is very crucial to such analysis. In such certifications/validation a fixed data pattern is transmitted from the scope and received back. Example of such patterns is PRBS. Eye diagram basically is a voltage/time samples of the actual data. the eye diagram is representation of some million samples of data patterns captured. Oscilloscope is to be used in persistence mode to capture the sequence of samples.

What can be measured using an eye diagram?

1. Rise Time

2. Fall Time

3. Jitter

4. Over shoot

5. undershoot

6. Bit error rate

7. Cross talk

8. Inter symbol interference

9. Signal-to-Noise Ratio

What do we do/How do we analyze using eye diagram?

1. When we are measuring a interface performance, like for example, USB, we have to determine the acceptable levels of signal that help for exact reproduction of the signal at the receiver. For this we draw a small diagram called eye mask. If the generated eye diagram is well beyond this eye mask, then channel is performing well and doesn't have any signal integrity issues. If any of the eye diagram overlaps eye mask then there is a serious issue in the channel.

2. An eye opening (so called height of the eye or peak-to-peak value) is an indication of the channel performance. If an eye diagram generated is observed to be closed, then there is signal integrity issue in the channel.

3. The overshoot and undershoot indicates the impedance mismatch that is present in the channel because of which reflections occurred.

4. The eye width indicates the unit interval, and is an indication of any jitter present in the channel.

The basic test setup for generating eye diagram is:

The following image is a capture of eye diagram. Snapshot is taken from edn.com/keysight.com to give a view of the eye diagram analysis and capture.

Definitions used in eye diagram:

One level: The highest level (logic high voltage) in a peak-to-peak representation of the signal

Zero level: The lowest level (logic low voltage) in a peak-to-peak representation of the signal

Amplitude: The difference between one level and zero level.

Eye Height: Indication of eye opening. Under ideal conditions, Amplitude is equal to eye height. 

Eye crossing: Indication of jitter that is present in the channel.

Disadvantages of eye diagram:

1. Eye diagram can only judge but can't guarantee the channel performance.

2. Eye diagram is generally captured with a standard data pattern but in real time the pattern can vary.

3. Eye diagram can't determine the actual cause of the signal degradation in the channel.

Analog Circuits - Logarithmic Amplifier

There are various applications of op-amps. One of the important circuits using op-amp circuits is logarithmic amplifier. In logarithmic amplifier, the output is natural log of input signal.  the input signal can be a simple voltage. The basic equation that describes the logarithmic amplifier output is,

Vout = K * ln (Vin), K is gain of logarithmic amplifier

As we are saying logarithmic, this op-amp circuit is non-linear. So, a logarithmic amplifier converts linear voltage to non-linear. The main advantage of logarithmic amplifier is the dynamic range compression. So, if we have a very large dynamic range, it can be manipulated using a logarithmic amplifier.

The basic logarithmic amplifier circuit with diode is:

The basic electronic devices that help achieve logarithmic function are diodes and transistors. In a transistor, Vbe is related to Ic in a logarithmic way.

Output = -V_T ln(Input/I_s*R)

V_T  Thermal Voltage of the diode

 I_s    Saturation current in the diode

The reverse saturation current of the diode is temperature dependent.

Another logarithmic amplifier circuit with transistor is:

Some important points about logarithmic amplifier:

1. The gain of an ideal logarithmic amplifier approaches infinity as input approaches zero.

2. 

3. Change in output of logarithmic amplifier is the function of change in input voltage

3. Intercept voltage: The voltage at which the logarithmic value leads to zero. 

4. For smaller inputs, logarithmic amplifiers behave linear. The relation between input and output is linear.

Circuit by explanation: If i want to product of two analog signals, for suppose X and Y, we can do it using the below equation,

X * Y = Loginv(LOG(X)+Log(Y))

The above equation when represented in the form of block diagram, 

Application of logarithmic amplifiers:

1. Industrial circuits

     a. Process control

2. RF circuits

     a. Compression and decompression

     b. True RMS detection

Some vendors of logarithmic amplifiers used across different verticals of the industry are:

Texas Instruments - ADL5513 (Example of ic that is used in RF transmitter circuits)

Analog Devices - AD8307 (used in network and spectrum analyzers)

Maxim Integrated - MAX4206 (industrial applications)

Note: The reverse of logarithmic amplifier is anti-log amplifier where the non-linear signal is converted to linear signal.

High speed Designs - Part 1

A signal can be considered high speed, if the signal frequency that need be transmitted approaches 100MHz. There are many  parameters to decide if a signal can be considered high speed or not but let us for now consider 100MHz or greater frequency as high speed signal. When we talk in terms of bit rate it comes to 100Mbps if each cycle carries a single bit. as a straight forward definition, a signal can be treated as high speed if the speed is the major reason for the loss of the signal. Putting it the other way, the minimal frequency at which the signal starting degrading if improper care is not taken while routing it. All the frequencies above it are known as high speed frequencies. In another terms, frequency at which all the line parameters (R,L,C) are to be considered for analyzing the signal or the channel need to treated as transmission line can be called high speed signals.

                Routing a high speed signal is not so easy. There must be appropriate care taken starting from the PCB material selection to final routing stage. this implies from component selection, placement, stack up and routing each and every stage is critical in determining the quality of the board. We should take care that no signal integrity issues come up on the board. So, whether it is a high speed or low speed there are few factors that contribute to the loss of a signal on the PCB. The below are the list of items that are major contributors of loss in a PCB:

1. Package loss

2. Connector loss

3. Losses due to PCB traces (channel loss)

4. Losses due to via

The parasitics that the ic package introduces is the major contributor of losses. A package need to be treated as electrical model as such a model behavior need to be used in simulations. Consider, the electrical model of any ic (Ex: .ibis models), they list the R,L,C of the package pins. The Power distribution network of these ics and the modelling of these package connectivity is very crucial in signal integrity simulations.

Connectors are a must on any PCB to connect the board to the external world. Connectors are not always ideal. The characterization of the connector determines the accuracy of loss calculation. It is always preferable to select a low loss connector for high frequency designs.

The Channel loss or the PCB trace loss is due to 2 main factors: PCB material selection, PCB routing. The PCB material (dielectric material) is the crucial selection factor for high speed board designs. It is preferable to have a low loss dielectric for high speed signals. Also, narrower the PCB traces, higher the losses. Have as much wider trace as possible for lower losses. Again there is a trade-off between PCB material to be used, impedance of the board, width of the trace. The designer needs to make a careful selection to have a lowest loss signal.

Vias are one of the major loss on the PCB. Vias are the main reason for discontinuities on the board. The via type selection is vital at the preliminary stages of the high speed design. The types that can be used are blind via, buried via, micro via, differential vias.  Back drilling is used in some boards in case of micro vias to reduce losses. The via length in these cases is the major loss contributor. The return path for the signal path which has vias is very crucial for maintaining the integrity of the signal. If the vias are not laid properly, the introduced noise may cause substantial damage to the end product in use causing endless breakdowns. The via annular ring need to be designed after considering the amount of loss that is tolerated.

If you are working on high speed board, these PCB factors are very important and some designers calculate the loss budget with these parameters before proceeding with the manufacturing. Loss budget in these cases is the sum of the loss parameters (Connector loss, via losses, PCB trace losses, package parasitic losses) that we have talked of here.

Soldering Machines

This post is written on the request of one of the reader of our blog. thanks for the mail, it encourages us to write more articles when readers request for more.

Soldering is a process which is used to join two materials using a joint. The joint usually called a soldering material which has a lower melting point. Soldering machines are the tools used to do the soldering process. One more material used during the soldering process is the flux. Flux facilitates the soldering process. Soldering machines come in various shapes and sizes. It can be in the form of a gun or it can be in the form of a handle. A removable heat element at the tip of the machine facilitates soldering process. 

Temperature controlled or not?

The soldering machines are either temperature controlled or may be of fixed temperature. The temperature controlled soldering machines are a big set up and are commonly named soldering station. the soldering station is a combination of heat element, handle and a power supply regulation circuit. Soldering stations do have a display to read the tip temperature. A thermistor on the tip enables to read the temperature which is displayed on the screen.

Soldering iron power rating.

           Soldering machines are available in various power ratings. A machine with high power rating should not be used for minute joint soldering. That may damage the electronic components. Where as low power machines should be used for minute joints. the power ratings of the soldering machines range from 10-50W.

Soldering iron tip

Generally called a bit which can be detachable and comes in various sizes. The size is determined by the size of the joint that must be soldered. There are various tip sizes available. A slanted tip at the edge may have a more heat holding capability where as straight bits have less heat holding capability.

Various vendors who provide soldering machines:

METCAL

SOLDRON

ADVANCETECH

MAX TECHNOLOGY

METROQ

Wetting current (Sealing current)

Switches/Relays require some initial current to break the oxidation layer that is formed across the contacts. Supplying this amount of current helps the contact form reliably. The current supplied heats the oxide layer. This amount of current is obviously an additional burden on your power circuit but is the minimum current required to form a contact. Oxidation generally happens in humid conditions where the oxide layer is formed across the joints. The oxidation can generally be treated as resistance when you speak as an electrical engineer. The scenario of wetting current can be seen in the case of switches where you provide the stimulus but still doesn't turn up, where little more current would have been required there. Generally, in the humidity tests, these kind of issues come up on the board. The amount of whetting current depends on the material that is used for the contacts. For example, a gold plated contact may form a reliable contact with less wetting current. the two generic circuit parameters you may across in this scenario are punch through and stand-off voltage. Stand-off voltage is the minimum voltage that need to be provided for the oxide layer to break through. 

Dithering in circuits

Are you designing a board which requires agency certifications? Do you want to control any EMI/EMC concerns that are arising out of power supply section. One way to address your concerns is dithering of power supply. You might have taken proper concerns in layout but sometimes the power supply may be the source of noise in spite of extreme care taken in design. Dithering is nothing but a small electronic circuit to control the switching frequency of the power supply. The frequency spectrum of the oscillator can be spread to increase the band of frequency. Frequency spread meant distributing the total energy among the multiples of fundamental frequency. The dithering circuit is a simple op-amp circuit controlling the voltage into one of the frequency determining pin of the switching power supply. The voltage on this pin of switcher determines the frequency of operation of the switcher. Have you ever used a spectrum analyzer to probe a frequency generator in the circuit? If you try to probe the signal, you see a peak at the fundamental frequency of the switcher but if the signal is measured with dithering applied we can see the signal distributed over a band of frequencies. This technique can also be said as spread spectrum where the frequency is spread over a band.

PCB Routing guidelines - Part 1 (Power Supply)

Power supply design is one of the critical factor in circuit design. Designer may design a flawless design but if they don't give sufficient guidelines to the layout engineer or if the layout engineer doesn't follow the appropriate guidelines the whole effort to put in during the design phase may be wasted. Whether you are working with AC or DC, or whether you are working with linear supply or switching regulator, following the recommended guidelines is a must. The thermal performance, functional qualification, certification (EMI/EMC) depends on the proper layout of power supply also. Finally, a good stable power supply is a result of good layout design practices. We always have to 

remember that switching power supplies are the main sources of EMI in the circuits as they contain the switching elements. Based on the switching that is happening in the switching mode power supply the noise is either radiated or coupled to other circuits. 

The collection of layout guidelines that need to be followed by the layout engineer are listed below.

1. Have a separate plane for power and signals. 

2. Isolate the power and signal planes with continuous ground plane.

Note: For the above two points we are talking about the multi-layer boards.

3. The ground path loop should be as small as possible. 

4. Have a complete copper pour underneath the switcher/linear regulator and connect this to thermal pad. This helps to sink the heat to the PCB.

5. Placement is very critical in regulators. Placement must be in such a way that all the components should not be distributed randomly.

Note: For the above point reason is that the return current should not change direction.

6. Never try to connect the grounds in a daisy chaned way. The noise on one circuit may propogate to other easily. Try to use a star type routing for ground. 

7. Isolate the signal and power grounds and have a common node for connecting all together. 

8. Place the capacitors at the input and output of regulator as close as possible. 

Reason: The additional trace acts as inductor affecting the transient response of the switcher.

9. The grounding of the capacitor should be as close as possible to the supply regulator. Avoid longer ground traces. Having a lesser ground trace lengths help to eliminate the unnecessary ground loops.

10. The most important point to remember is that layout engineer should always know the amount of current that flows on the power traces. Correspondingly, the width of the must be layout. 

11. When there are via to connect different points of the circuit, have sufficient stitching via to support desired current.

12. The power trace connecting the various points should not be free flown. The length should be maintained as short as possible.

13. The board will have signal traces and power traces as well. Power traces should be maintained thicker to allow sufficient current to flow. Irrespective of lowest current limit, the power trace should be > 12mils always and further based on current flow, the width will change.

14. Switching regulators have a inductor at their output, take care that you don't route the low power traces near the inductor. 

15. The placement of digital circuit must be such a way that they should be placed away from the inductor.

Reason: The reason for the above two points is that inductors are the source of EMI on the boards.

16. The feedback path in the regulator is very critical to determine the output of regulator. Try to keep the resistive dividers in the feedback path as close as possible to the feedback pin. If not possible, route the feedback trace thicker. 

17. The feedback trace must be away from all the noisy paths. If required provide ground isolation to the feedback paths from other circuits/traces.

18. The components at the output of regulator (inductor, capacitor, schottky) should be placed as much closer as possible. 

19. Have a perfect ground plane around and underneath the regulator. This helps any EMI from the power circuit to ground directly.

What are the effects of bad layout? The effects of layout are more seen as the load current is more.

1. Desired regulation may not happen.It meant the output may vary from the desired output.

2. Too much noise at the output of the regulator.

3. Increases design iterations and hence increases project cost.

4. Has to have a good mechanical design to compensate for bad layout practices.

5. Ground bounce leading to improper ground reference.

6. Simultaneous switching noise affecting signal integrity.

"Free Synch" in displays

Refresh rate is one of the most important specification of monitors. Monitors often refresh their buffers at a standard rate. This for the displays is constant at 60Hz. But these days displays are coming up with different refresh rates which is going up to 120Hz. Also, that the refresh rate can be varied dynamically based on activities on the display. These days the graphics processors are becoming performance intensive with extreme stress on display technologies. the display should sync w.r.t graphics capability of processor else you may see monitor breaking down in extreme cases (like for example take the case of high end gaming). To eliminate this sync issues, AMD came with a new technology called free sync where the refresh rate of display can be varied as per the performance requirement. Let us assume a case where there is no activity on the display, in such a case refresh rate can be reduced to lowest, thus, helping in lower power consumption. Screen-tear is one of the problems seen in high end gaming where the screen is overlapped or occupied by the previous screen. Free sync is enabled on display port with capability of performing in extremely performance intensive applications. Most of the PC games demand change in frame rates and free sync helps to compensate as per demand. The older v-sync process can't be used here as the frame expectation is different from graphical processor and display technology.

        Free sync from AMD is similar to the G-sync from Nvidia. There is a compability issue here. To take advantage of G-sync both the display and GPU should have that technology. This doesn't mean that a G-sync can't be used with normal processors. R9 series from AMD is one example which has the Free sync technology. 

Latch Up

Have you ever faced a situation in which a component fails immediately after power up? or did you observe your circuit recovering after power cycle? Then you might have observed the latch up condition unknowingly. Latch up occurs when unintentional low impedance path is formed in the digital circuits of a integrated circuit. The integrated circuit is generally built with mosfet structures. So, most of the latch issues are seen in CMOS logic. The parasitic paths formed within the mosfet structure leads to high current and hence damage the mosfet.

To explain it more from the mosfet structure, latch is the generation of a low-impedance path in integrated chip between the power supply and the ground rails due to interaction of parasitic pnp and npn bipolar transistors. One has to remember that the circuit designer using CMOS logic integrated circuit can't avoid latch up as this can be eliminated only when integrated circuit physical design is done.

Have you tried power sequencing in a circuit, or tried power states in the board? During these conditions, we will try to power on/power off various circuits on the board. In that case, when signals are applied at the input of unpowered CMOS circuit, latch up occurs, where the unintentional current may be transferred. Latch up may also occur when the signals applied to a CMOS logic cross the power thresholds. 

Inrush current limit - Part 1

Are you expecting inrush current in your circuit? or have you heard you heard about the surge current? Have you ever dealt with surge current? Are you a beginner and don't know what component/circuit to use? Then after reading this article you must be able to decide after need to be done. Also, if we see our SMPS designs, inrush current limiter is commonly used.

             To start this discussion, let us take a scenario when we power on the circuit. Initially, there will be a surge current that flows. This is because of the capacitor bank that is present in the circuit which draw a significant current instantaneously to charge themselves. Also, we can put it the other way, when the current drawn by the load is greater than steady state current of the circuit, it is called surge current. Surge current may not be significant in some cases. This depends on the underlying circuitry used. If the surge current is of small duration such that the circuitry doesn't get affected by it, then we need not have any protection. Also, the affect of surge current may not be straight forward, it may reduce the life time of a component. The graph here shows the surge current drawn in a circuit over a time.

                 The tradition way of limiting the current is to use a fuse to limit the current. But if the current exceeds the fuse limit, then fuse blows off and only way to recover the circuit functionality is to replace the fuse with a new one. But this is a tedious job. One way to avoid fuse blow is to use some other circuit which handles the inrush current. Thermistor is one such component. we always use resistors in circuits to limit the current, for example, if we take the case of LED, it is always preferable to use a series resistor. But series resistor will not suffice if the inrush current is in amperes range and in fact the resistor may blow away. Also, resistors doesn't have the property to change their resistance unlike thermistor. Thermistors are better suited for these applications.

Thermistors are of type positive temperature co-efficient (PTC) and negative temperature co-efficient (NTC). NTC type are used as inrush current limiters. NTC thermistors are designed to be used in inrush limiter circuits. The principle of NTC is that resistance decreases with increase in temperature. so, initially, thermistor has very high resistance. As the current starts flowing, the resistance decreases as drop/temperature increases. 

     Using thermistor is also a cheaper option rather than having a complex circuitry (Active circuit) to limit the current. NTC is the most commonly used in the industry. 

General specifications to be checked while selecting a NTC/PTC as current limiter:

1. Resistance offered vs temperature 

2. Hold current (current at which thermistor provides low resistance)

3. Trip current (the current at which the thermistor offers high resistance)

4. Recovery time (for thermistor to come back to high resistance after the circuit has switched off)

Advantages of using thermistors:

1. Reliable

2. Stable

3. Lower cost

4. Lesser footprint

5. Easy to include in the circuit and easy to select

6. Longer life time

Some of the disadvantages of using inrush current protection:

1. When thermistor is used, there will be a voltage drop across it.

2. For a small form factor boards, with sizable power consumption (current draw by load), we need to include a bigger size thermistor which may be a limiting factor

3. High recovery time for thermistors.

Important points of thermistor as Inrush current limiter:

1. Resistance drops to milli ohms within in milliseconds

2. The resistance offered by thermistor during idle state will be in hundreds of ohms.

How to select the resistance of inrush current limiter?

Let us assume that we have a circuit with input voltage 12V and load current of 1A. In such cases, the value of thermistor is selected such that it allows min. 1A and cuts off above that current. So, here resistance if V/I = 12 ohms. So, have a thermistor of at least 12 ohms.