Latch Up

Have you ever faced a situation in which a component fails immediately after power up? or did you observe your circuit recovering after power cycle? Then you might have observed the latch up condition unknowingly. Latch up occurs when unintentional low impedance path is formed in the digital circuits of a integrated circuit. The integrated circuit is generally built with mosfet structures. So, most of the latch issues are seen in CMOS logic. The parasitic paths formed within the mosfet structure leads to high current and hence damage the mosfet.

To explain it more from the mosfet structure, latch is the generation of a low-impedance path in integrated chip between the power supply and the ground rails due to interaction of parasitic pnp and npn bipolar transistors. One has to remember that the circuit designer using CMOS logic integrated circuit can't avoid latch up as this can be eliminated only when integrated circuit physical design is done.

Have you tried power sequencing in a circuit, or tried power states in the board? During these conditions, we will try to power on/power off various circuits on the board. In that case, when signals are applied at the input of unpowered CMOS circuit, latch up occurs, where the unintentional current may be transferred. Latch up may also occur when the signals applied to a CMOS logic cross the power thresholds.