MBlaze 3G settings for ZEN A10 ULTRATAB

I bought a ZEN A10 Ultra tab. It does not support simcard, so, had to do with either external modem (2G or 3G) or a Wi-Fi. Had to browse a bit to find the correct settings. Here i have included the procedure for your reference.

For dongle to work, you have to set Access point names.Plug-in the dongle and do the following:

Go to settings->More->Mobile networks->click on Access point names. If your dongle is already connected it automatically configures MCC and MNC. Then change other parameters as following:

APN: #777
USERNAME: internet@internet.mtsindia.in
PASSWORD: MTS
APN TYPE: Leave this blank (don't set anything here)
NAME: MTS
PROXY: Leave this blank (don't set anything here)
PORT: Leave this blank (don't set anything here)
SERVER: Leave this blank (don't set anything here)
MMSC: Leave this blank (don't set anything here)
MMS PROXY: Leave this blank (don't set anything here)
MMS PORT: Leave this blank (don't set anything here)
AUTHENTICATION TYPE: PAP or CHAP
APN PROTOCOL: IPv4/IPv6
BEARER: unspecified

I also found this video, which helps how to go to APNs and set them:
www.youtube.com/watch?v=SH4L_aPZiBg

Some points to note:
1. This supports only CDMA (TATA/RELIANCE/MTS).
2. When you plug-in a dongle, it automatically configures MNC/MCC
3. Once you are done with settings, wait for sometime until a network connectivity symbol comes up on the right corner of your tablet. Once, it comes, you can browse.

The only mistake i did was, i have set everything correctly and started browsing instantly. Never waited for network connectivity symbol and was disappointed buying this product. But once it got connected, i am feeling ZEN A10 ULTRA TAB is one of the good tablets in markets. Even battery backup seems good. They specify a power cycle and i followed it, and now i get a 2.30 hours back up even though i use it continuously.

Working startup.s file for LPC2148

Recently, i was working on LPC2148 development board and was in need of startup file. I tried to include the file which keil environment generates automatically and it never worked. Had to browse a lot to find a working file. Here i am putting in the blog for your quick reference. Hope, it helps someone there!!! Copy from the first line till end and paste it in your startup.s file.

;/*
; *  The STARTUP.S code is executed after CPU Reset. This file may be
; *  translated with the following SET symbols. In uVision these SET
; *  symbols are entered under Options - ASM - Define.
; *
; *  REMAP: when set the startup code initializes the register MEMMAP
; *  which overwrites the settings of the CPU configuration pins. The
; *  startup and interrupt vectors are remapped from:
; *     0x00000000  default setting (not remapped)
; *     0x80000000  when EXTMEM_MODE is used
; *     0x40000000  when RAM_MODE is used
; *
; *  EXTMEM_MODE: when set the device is configured for code execution
; *  from external memory starting at address 0x80000000.
; *
; *  RAM_MODE: when set the device is configured for code execution
; *  from on-chip RAM starting at address 0x40000000.
; */


; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F

I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled


;// <h> Stack Configuration (Stack Sizes in Bytes)
;//   <o0> Undefined Mode      <0x0-0xFFFFFFFF:8>
;//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF:8>
;//   <o2> Abort Mode          <0x0-0xFFFFFFFF:8>
;//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF:8>
;//   <o5> User/System Mode    <0x0-0xFFFFFFFF:8>
;// </h>

UND_Stack_Size  EQU     0x00000000
SVC_Stack_Size  EQU     0x00000008
ABT_Stack_Size  EQU     0x00000000
FIQ_Stack_Size  EQU     0x00000000
IRQ_Stack_Size  EQU     0x00000080
USR_Stack_Size  EQU     0x00000400

Stack_Size      EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
                         FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size)

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size

Stack_Top       EQU     Stack_Mem + Stack_Size


;// <h> Heap Configuration
;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>

Heap_Size       EQU     0x00000000

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem        SPACE   Heap_Size


; VPBDIV definitions
VPBDIV          EQU     0xE01FC100      ; VPBDIV Address

;// <e> VPBDIV Setup
;// <i> Peripheral Bus Clock Rate
;//   <o1.0..1>   VPBDIV: VPB Clock
;//               <0=> VPB Clock = CPU Clock / 4
;//               <1=> VPB Clock = CPU Clock
;//               <2=> VPB Clock = CPU Clock / 2
;//   <o1.4..5>   XCLKDIV: XCLK Pin
;//               <0=> XCLK Pin = CPU Clock / 4
;//               <1=> XCLK Pin = CPU Clock
;//               <2=> XCLK Pin = CPU Clock / 2
;// </e>
VPBDIV_SETUP    EQU     1
VPBDIV_Val      EQU     0x00000011


; Phase Locked Loop (PLL) definitions
PLL_BASE        EQU     0xE01FC080      ; PLL Base Address
PLLCON_OFS      EQU     0x00            ; PLL Control Offset
PLLCFG_OFS      EQU     0x04            ; PLL Configuration Offset
PLLSTAT_OFS     EQU     0x08            ; PLL Status Offset
PLLFEED_OFS     EQU     0x0C            ; PLL Feed Offset
PLLCON_PLLE     EQU     (1<<0)          ; PLL Enable
PLLCON_PLLC     EQU     (1<<1)          ; PLL Connect
PLLCFG_MSEL     EQU     (0x1F<<0)       ; PLL Multiplier
PLLCFG_PSEL     EQU     (0x03<<5)       ; PLL Divider
PLLSTAT_PLOCK   EQU     (1<<10)         ; PLL Lock Status

;// <e> PLL Setup
;//   <o1.0..4>   MSEL: PLL Multiplier Selection
;//               <1-32><#-1>
;//               <i> M Value
;//   <o1.5..6>   PSEL: PLL Divider Selection
;//               <0=> 1   <1=> 2   <2=> 4   <3=> 8
;//               <i> P Value
;// </e>
PLL_SETUP       EQU     1
PLLCFG_Val      EQU     0x00000024


; Memory Accelerator Module (MAM) definitions
MAM_BASE        EQU     0xE01FC000      ; MAM Base Address
MAMCR_OFS       EQU     0x00            ; MAM Control Offset
MAMTIM_OFS      EQU     0x04            ; MAM Timing Offset

;// <e> MAM Setup
;//   <o1.0..1>   MAM Control
;//               <0=> Disabled
;//               <1=> Partially Enabled
;//               <2=> Fully Enabled
;//               <i> Mode
;//   <o2.0..2>   MAM Timing
;//               <0=> Reserved  <1=> 1   <2=> 2   <3=> 3
;//               <4=> 4         <5=> 5   <6=> 6   <7=> 7
;//               <i> Fetch Cycles
;// </e>
MAM_SETUP       EQU     1
MAMCR_Val       EQU     0x00000002
MAMTIM_Val      EQU     0x00000004


; External Memory Controller (EMC) definitions
EMC_BASE        EQU     0xFFE00000      ; EMC Base Address
BCFG0_OFS       EQU     0x00            ; BCFG0 Offset
BCFG1_OFS       EQU     0x04            ; BCFG1 Offset
BCFG2_OFS       EQU     0x08            ; BCFG2 Offset
BCFG3_OFS       EQU     0x0C            ; BCFG3 Offset

;// <e> External Memory Controller (EMC)
EMC_SETUP       EQU     0

;//   <e> Bank Configuration 0 (BCFG0)
;//     <o1.0..3>   IDCY: Idle Cycles <0-15>
;//     <o1.5..9>   WST1: Wait States 1 <0-31>
;//     <o1.11..15> WST2: Wait States 2 <0-31>
;//     <o1.10>     RBLE: Read Byte Lane Enable
;//     <o1.26>     WP: Write Protect
;//     <o1.27>     BM: Burst ROM
;//     <o1.28..29> MW: Memory Width  <0=>  8-bit  <1=> 16-bit
;//                                   <2=> 32-bit  <3=> Reserved
;//   </e>
BCFG0_SETUP EQU         0
BCFG0_Val   EQU         0x0000FBEF

;//   <e> Bank Configuration 1 (BCFG1)
;//     <o1.0..3>   IDCY: Idle Cycles <0-15>
;//     <o1.5..9>   WST1: Wait States 1 <0-31>
;//     <o1.11..15> WST2: Wait States 2 <0-31>
;//     <o1.10>     RBLE: Read Byte Lane Enable
;//     <o1.26>     WP: Write Protect
;//     <o1.27>     BM: Burst ROM
;//     <o1.28..29> MW: Memory Width  <0=>  8-bit  <1=> 16-bit
;//                                   <2=> 32-bit  <3=> Reserved
;//   </e>
BCFG1_SETUP EQU         0
BCFG1_Val   EQU         0x0000FBEF

;//   <e> Bank Configuration 2 (BCFG2)
;//     <o1.0..3>   IDCY: Idle Cycles <0-15>
;//     <o1.5..9>   WST1: Wait States 1 <0-31>
;//     <o1.11..15> WST2: Wait States 2 <0-31>
;//     <o1.10>     RBLE: Read Byte Lane Enable
;//     <o1.26>     WP: Write Protect
;//     <o1.27>     BM: Burst ROM
;//     <o1.28..29> MW: Memory Width  <0=>  8-bit  <1=> 16-bit
;//                                   <2=> 32-bit  <3=> Reserved
;//   </e>
BCFG2_SETUP EQU         0
BCFG2_Val   EQU         0x0000FBEF

;//   <e> Bank Configuration 3 (BCFG3)
;//     <o1.0..3>   IDCY: Idle Cycles <0-15>
;//     <o1.5..9>   WST1: Wait States 1 <0-31>
;//     <o1.11..15> WST2: Wait States 2 <0-31>
;//     <o1.10>     RBLE: Read Byte Lane Enable
;//     <o1.26>     WP: Write Protect
;//     <o1.27>     BM: Burst ROM
;//     <o1.28..29> MW: Memory Width  <0=>  8-bit  <1=> 16-bit
;//                                   <2=> 32-bit  <3=> Reserved
;//   </e>
BCFG3_SETUP EQU         0
BCFG3_Val   EQU         0x0000FBEF

;// </e> End of EMC


; External Memory Pins definitions
PINSEL2         EQU     0xE002C014      ; PINSEL2 Address
PINSEL2_Val     EQU     0x0E6149E4      ; CS0..3, OE, WE, BLS0..3,
                                        ; D0..31, A2..23, JTAG Pins


                PRESERVE8
             

; Area Definition and Entry Point
;  Startup Code must be linked first at Address at which it expects to run.

                AREA    RESET, CODE, READONLY
                ARM


; Exception Vectors
;  Mapped to Address 0.
;  Absolute addressing mode must be used.
;  Dummy Handlers are implemented as infinite loops which can be modified.

Vectors         LDR     PC, Reset_Addr      
                LDR     PC, Undef_Addr
                LDR     PC, SWI_Addr
                LDR     PC, PAbt_Addr
                LDR     PC, DAbt_Addr
                NOP                            ; Reserved Vector
;               LDR     PC, IRQ_Addr
                LDR     PC, [PC, #-0x0FF0]     ; Vector from VicVectAddr
                LDR     PC, FIQ_Addr

Reset_Addr      DCD     Reset_Handler
Undef_Addr      DCD     Undef_Handler
SWI_Addr        DCD     SWI_Handler
PAbt_Addr       DCD     PAbt_Handler
DAbt_Addr       DCD     DAbt_Handler
                DCD     0                      ; Reserved Address
IRQ_Addr        DCD     IRQ_Handler
FIQ_Addr        DCD     FIQ_Handler

Undef_Handler   B       Undef_Handler
SWI_Handler     B       SWI_Handler
PAbt_Handler    B       PAbt_Handler
DAbt_Handler    B       DAbt_Handler
IRQ_Handler     B       IRQ_Handler
FIQ_Handler     B       FIQ_Handler


; Reset Handler

                EXPORT  Reset_Handler
Reset_Handler


; Setup External Memory Pins
                IF      :DEF:EXTERNAL_MODE
                LDR     R0, =PINSEL2
                LDR     R1, =PINSEL2_Val
                STR     R1, [R0]
                ENDIF


; Setup External Memory Controller
                IF      EMC_SETUP <> 0
                LDR     R0, =EMC_BASE

                IF      BCFG0_SETUP <> 0
                LDR     R1, =BCFG0_Val
                STR     R1, [R0, #BCFG0_OFS]
                ENDIF

                IF      BCFG1_SETUP <> 0
                LDR     R1, =BCFG1_Val
                STR     R1, [R0, #BCFG1_OFS]
                ENDIF

                IF      BCFG2_SETUP <> 0
                LDR     R1, =BCFG2_Val
                STR     R1, [R0, #BCFG2_OFS]
                ENDIF

                IF      BCFG3_SETUP <> 0
                LDR     R1, =BCFG3_Val
                STR     R1, [R0, #BCFG3_OFS]
                ENDIF

                ENDIF   ; EMC_SETUP


; Setup VPBDIV
                IF      VPBDIV_SETUP <> 0
                LDR     R0, =VPBDIV
                LDR     R1, =VPBDIV_Val
                STR     R1, [R0]
                ENDIF


; Setup PLL
                IF      PLL_SETUP <> 0
                LDR     R0, =PLL_BASE
                MOV     R1, #0xAA
                MOV     R2, #0x55

;  Configure and Enable PLL
                MOV     R3, #PLLCFG_Val
                STR     R3, [R0, #PLLCFG_OFS]
                MOV     R3, #PLLCON_PLLE
                STR     R3, [R0, #PLLCON_OFS]
                STR     R1, [R0, #PLLFEED_OFS]
                STR     R2, [R0, #PLLFEED_OFS]

;  Wait until PLL Locked
PLL_Loop        LDR     R3, [R0, #PLLSTAT_OFS]
                ANDS    R3, R3, #PLLSTAT_PLOCK
                BEQ     PLL_Loop

;  Switch to PLL Clock
                MOV     R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
                STR     R3, [R0, #PLLCON_OFS]
                STR     R1, [R0, #PLLFEED_OFS]
                STR     R2, [R0, #PLLFEED_OFS]
                ENDIF   ; PLL_SETUP


; Setup MAM
                IF      MAM_SETUP <> 0
                LDR     R0, =MAM_BASE
                MOV     R1, #MAMTIM_Val
                STR     R1, [R0, #MAMTIM_OFS]
                MOV     R1, #MAMCR_Val
                STR     R1, [R0, #MAMCR_OFS]
                ENDIF   ; MAM_SETUP


; Memory Mapping (when Interrupt Vectors are in RAM)
MEMMAP          EQU     0xE01FC040      ; Memory Mapping Control
                IF      :DEF:REMAP
                LDR     R0, =MEMMAP
                IF      :DEF:EXTMEM_MODE
                MOV     R1, #3
                ELIF    :DEF:RAM_MODE
                MOV     R1, #2
                ELSE
                MOV     R1, #1
                ENDIF
                STR     R1, [R0]
                ENDIF


; Initialise Interrupt System
;  ...


; Setup Stack for each mode

                LDR     R0, =Stack_Top

;  Enter Undefined Instruction Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #UND_Stack_Size

;  Enter Abort Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #ABT_Stack_Size

;  Enter FIQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #FIQ_Stack_Size

;  Enter IRQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #IRQ_Stack_Size

;  Enter Supervisor Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #SVC_Stack_Size

;  Enter User Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_USR
                MOV     SP, R0
                SUB     SL, SP, #USR_Stack_Size


; Enter the C code

                IMPORT  __main
                LDR     R0, =__main
                BX      R0


; User Initial Stack & Heap
                AREA    |.text|, CODE, READONLY

                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap
__user_initial_stackheap

                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + USR_Stack_Size)
                LDR     R2, = (Heap_Mem +      Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR


                END

Schottky diode

Consider, a case where you want to isolate a battery supply with mains supply or incase you want to isolate two supplies, schottky diode is suitable for this application.

Schottky diode or surface barrier diode or hot carrier diode is a majority carrier, metal-semiconductor junction diode with very less reverse recovery time. The reverse recovery time is in picosec as compared to normal diodes that have reverse recovery in nanosec. Schottky conduts when forward biased. In many applications, we see schottky diode used in series with supply. Another advantage of schottky is less EMI noise. For normal diodes due to some reverse current flowing, in high-power applications EMI noise is a problem.

Advantages:
1. Less reverse recovery time and hence fast switching
2. Low EMI noise and hence preferred for high frequency applications
3. Smaller device area
4. Low forward drop (0.15 to 0.45V)
5. Low junction capacitance
6. High current density
7. Less power dissipation and hence small size heat sinks in high power applications

Disadvantages:
1. Low reverse voltage rating
2. Reverse current variation with temperature

Applications:
1. RF detector
2. Switching regulators
3. Diode mixer
4. Solar cell

SMBus versus I2C

Did you hear about Smart Battery system (SBS)? Or did you at least see a system in which you get a display of battery manufacturer, type, model number, discharge rate, remaining capacity? If your answer is yes, then you must have listened about SMBus too.  SMBus is the underlying bus used for communication with power sources like battery. The modern smart batteries have an integrated circuit which communicates with the processor over SMBus sending the required battery data.

SMBus defined by INTEL is a 2-wire protocol like I2C. It can be said like a low speed bus and operates over a range of 10-100 KHz. In other words, SMBus is used for Low-Bandwidth applications. The latest PMBus extends the speed to 400 KHz. Like I2C, SMBus also has open collector configuration and all the hardware design considerations are similar. The pull-up requirements are not that stringent compared to I2C. The data transfer formats of SMBus are a subset of I2C data transfer formats. Modern embedded systems which use PMICs for power sequencing and handling also use SMBus for communication.

Let us assume, a slave is busy with some real-time processing and master sends a request for communication. The slave keeps the clock low until it completes its routines and takes up the request later. This is the case with I2C. That is why I2C bus is also sometimes called “DC bus”. In this case, the I2C bus may be held up until slave is serviced. Where as in the case of SMBus, there is a time up after which the master recognizes that there is a problem on the other end and stops the communication. It may also send the reset signal to slave.

Electrical levels over SMBus:

The fixed low/high voltage levels of SMBus are 0.8V/2.1V (1.5/3V for I2C).

Sink current: 100-300uA (3mA for I2C)

From the sink current specifications, it is clear that SMBus uses weak pull-up resistors.

Are SMBus and I2C compatible?

SMBus and I2C can work together on same bus but with some constraints:

Ø  Due to time out constraint, SMBus cannot operate under 10 KHz. Whereas I2C can be called a DC bus and can operate from 0 Hz.

Ø  For I2C and SMBus, the sink current requirements vary and if both are to compatible, the pull-up resistors need to be selected carefully.

Ø  Although, voltage swings as per electrical specifications vary, interchangeability can be done.

SMBALERT#:

SMBus in some application also has special alert signal which indicates the interrupt condition to the host. This signal is mainly used in PCI application. Some of the PCI add-in cards use SMBus for their communication and it is common to see SMBus signals defined in standard PCI connectors. The following pin out of PCIe x1 slot shows SMBus signals.

The below table shows a comparison of I2C and SMBus:

I2C	SMBus
Speed : 0-100 KHz 0-400 KHz 0-1 MHz 0-3.4 MHz	Speed: 10-100KHz
No time-out	Time-out of 35ms
Rise and Fall time not defined	Rise and Fall time defined
The time for which Slave and Master can hold clock low are not defined.	The time for which Slave and Master can hold clock low (SEXT, MEXT) are defined.
Hot plugging doesn’t work	Hot plugging works
For 7-bit addressing, 128 devices can be connected.	For 7-bit addressing, 128 devices can be connected.
Dynamic address allocation not possible.	Includes Address resolution protocol that can make dynamic address allocations.
Packet Error checking not included.	Packet Error checking included.
Error recovery impossible if Slave holds Data or Clock line low forever.	Error recovery possible after time out

What happens if data or Clock line is held low forever by slave?

This is an error condition in I2C, where master can’t handle. Slaves doesn’t generally doesn’t hold clock low and it is data line which can be held low for some time. The master has to keep sending clock signals over a time until slave pulls it high. Where as in SMBus, after a specific time, slave will be reset.

Applications of SMBus:

ü  Smart Batteries

ü  Power Management (PMICs)

ü  Communication with add-in cards of PCI

ü  Temperature, Voltage Sensors.

Understanding I2C - Part 3

Beginners need to know that I2C is a simple synchronous serial communication protocol.

I2C routing/external cable distance:

If you are routing I2C lines on PCB or using external cables, we have to keep in mind the maximum distance to which it can be done. Generally, without considering any factors, the length can be 9-12 feet. But length depends on following factors:

1.    Speed

2.    Load (capacitance)

3.    Source for pull-up

The distance can be increased by using a active current source instead of simple pull-up resistor. This is what is used in current amplifiers used as I2C repeater. For the same capacitance, I2C lines with repeater can be routed over longer distance than I2C lines with no repeater.

General Call in I2C:

In some cases, it is required that master need to communicate with all slaves at a time. In that case, Master has an option of sending “0000 0000” as address. This is called general call to which all the slaves will respond.

Multi Master Configuration:

Consider an application which demands two microcontrollers and ‘N’ number of sensors. This is a multi master application and clock need to be controlled carefully by either of the master. In this case, masters need to deal with Arbitration and Clock synchronization. Arbitration is like masters fighting for bus and one of them getting control at a specific time. Clock synchronization is like different masters may use different clocks and this can be differentiating factor in the case of slaves deciding which master has initiated the transaction. In case, a master doesn’t want to lose control of the bus, it may send repeated start bit in place of stop bit. This helps the master keep control of the bus. We need to remember that when a “START” signal is sent from Master to slave, the internal logic of slave is set to specific state. SCL need not ne bi-directional but in multi-master mode, the SCL needs to be bi-directional.

Genuine I2C routine:

DATA = 1;

CLK = 1; // initially CLK and DATA are high

Delay(n);

DATA = 0; // data made low from high to indicate START

Delay(n);

CLK = 0; // clock made low and in this state data bit can be put on the bus

Delay(n);

DATA = 0 or 1; // as, clock is made low, we are sending data byte

Delay(n);

CLK = 1; // Now clock is high and bit is freezed

Note: ‘n’ in delay function depends on clock cycle.

Understanding I2C - Part 2

I2C is a powerful serial communication used in data intensive applications. It replaces a complex parallel interface with a straight forward two-wire interface. Being a Master-Slave interface, each salve in I2C is addressable by a unique address. So, for a 7-bit address from master there can be 2^7 slaves on the line.  The addresses ranging from 0 to 127. The maximum slave count is sometimes limited by the capacitance over the bus. Designers need to keep in mind that for a capacitance of less than 200pf, pull-up is used and capacitance over 200pf requires a current source. The maximum capacitance over I2C as per the standard is 400pf.

How a START/STOP bit differs from other data bits transmission and how come slave differentiates between data and START/STOP bits?

During an I2C data transfer, when the CLK is HIGH, no transition must occur on SDA line. If such transition happens, then it is an indication of either a START/STOP condition.

1.       START condition is indicated by a HIGH to LOW transition when SCK is HIGH.

2.       STOP condition is indicated by a LOW to HIGH transition when SCK is HIGH.

UFm mode:

In Ultra-Fast mode, which can operate at a speed of up to 5Mbps, only unidirectional transfer is possible. There is no ACK from slave as in normal modes. It is a push-pull bus. PCx966x family (I2C bus controller) from NXP supports this ultra high speed I2C transfer.

Applications of I2C:

1.       LED controller/driver

2.       Touch interfaces for display

3.       GPIO Expanders

4.       Memory (EEPROM)

5.       RTC

6.       Gaming industry

7.       Sensors

8.       ADC/DAC

9.       Multiplexer/Switches

10.   Communication modules (BT, Wi-Fi, NFC, .. )

11.   Other control, portable and consumable applications

Advantages of I2C interface:

1.       Simple 2-wire serial interface

2.       Easily programmable

3.       I2C compared to other parallel interfaces reduces the PCB footprint and results in lower system costs.

What if you don’t have a I2C interface on your device?

An I2C bus controller can be used, to convert any of the parallel interfaces to I2C. MAX166x and PCx966x are some of the examples.

How do you simulate I2C data?

If you are working with a microcontroller, the debugging tools provided by that vendor help to trace the I2C data in registers. But if you have a standalone slave device evaluation board without any master and wanted to debug, TOTAL PAHSE provides some debugging tools which helps to simulate your I2C interface. Aardvark I2C/SPI Host Adapter from TOTAL PHASE acts as master and can pump in data to slave. Beagle I2C/SPI Protocol Analyzer helps to analyze the data transitions between them.

Understanding I2C - Part 1

I2C is a serial communication protocol. I2C uses SDA, SCL lines for communication. I2C was initially developed by Philips and is a famous protocol in embedded systems. Whether it may be microcontroller, processor, SoC or an FPGA, I2C interface is a must. I2C uses a 7-bit addressing scheme; also it uses 10-bit address. The data is transferred in bytes over SDA.

I2C uses a Master-Slave configuration with single master and multiple slaves. Also, there can be multiple masters over a link. At any time, only master can initiate a transfer and slave can only respond.  As I2C uses a 7-bit addressing scheme there can be 128 slaves connected over a I2C interface. As I2C transfers can take place only byte at a time, when master transfers a address an 8^th bit will be included which tells the slave whether it is a read or write cycle. A 8^th bit of ‘0’ indicates master writing to slave and ‘1’ indicates master reading from slave.

Depending on speed, three modes are defined in I2C communications:

Low speed mode – 10KHz

Standard mode – 100KHz

Fast Mode – 400KHz

High Speed Mode – 3.4MHz

Ultra Speed Mode – 5MHz (USDA, USCL)

The genuine doubt in the mind of embedded programmer comes in the case of data transfer to slave. For example, if a master wants to transmit 0x79 to slave, the master starts off the transmission from MSB of the byte. So, for 0x79 (01111001) , master transmits ‘0’, ‘1’, ‘1’, ‘1’, ‘1’, ‘0’… in sequence. But during data transfer there will be an extra bit from slave end indicating the status of data transfer, we call it ACK. If ACK from slave is ‘0’, it indicates that data is transferred successfully and ready to accept more. If ACK is ‘1’, data is transferred successfully and no more data to be transferred.

Why do I2C lines require pull-ups?

SDA, SCL are open drain drivers. So, master can drive low but to drive high an external pull-up is required on both SCL and SDA lines.

What is an open drain driver?

This open drain drivers discussion leads to a question of what is open drain driver, why can’t it drive high on it’s own. Going into the details, the I/O buffers on the master can be either open drain or push-pull. In a push-pull configuration, there will be two transistors where one drives the output low and the the other drives high. In a push-pull configuration, the lower transistor drives the output low and the upper transistor drives the output high. In an open drain configuration, there will be only one transistor which can drive the output low and when output must be high it can’t drive on it’s own and needs an external resistor. In TTL world, we call the same open driver as open collector.

What is clock stretching and arbitration in I2C?

Consider, a case in which two controllers are communicating with each other over a I2C line. When a master among it initiates a transfer, there might be case in which the other controller might be busy and it sees initiation from master and holds the SCL low until it finishes off it’s routines. This case of holding the SCL low is called clock stretching. During this time of SCL low, no communication can take place over I2C lines. Arbitration is another case in which SDA is held low.

How to choose a pull-up value for I2C lines?

Choosing I2C pull-ups is a challenge for any designer. Mostly, we go by the recommendations of the manufactures. For low frequency applications in the case of microcontrollers, we can by these recommendations. But in the case of high frequency applications, pull-ups need to be chosen after some study. The pull-up value depends on,

1.    Capacitance of the line.

2.    Length of the line

3.    Speed of transfer.

As the number of slaves over I2C line increases, the capacitance also increases. This capacitance includes capacitance at master, slave end and parasitic capacitance. As capacitance increases, time constant (RC) also increases. This increases the rise time and hence, speed reduces. This can be clearly seen when we probe the I2C lines. The signal tends to rise exponentially. This is not affordable and we have to bring back the square signal. For this as number of slaves increases, we tend to reduce the pull-up resistor value over the line. But there is a disadvantage in reducing pull-up because it causes more current to flow and hence unnecessary leakage and more power dissipation which is not acceptable for low power and battery powered applications. In such cases, only simulations will help to come to a correct solution before freezing off the design.

In case where I2C need to driven over a long distance, the parasitic capacitance will be high and hence we use lower pull-up values. Also, as the speed increases in the case of high speed and ultra high speed mode of I2C, the time constant must be low and hence we tend to use lower pull-up values.

The smallest value of I2C pull-up can be calculated using the formula,

              R(pull-up) = [V(pull-up) – (level over I2C lines)]/current from pull-up

The largest value depends on capacitance and speed of bus and can be calculated using,

              R(pull-up) = [1/Fmax]/Cbus

Cbus = Cmaster + Cslave + Cparasitic