PCB Routing guidelines - Part 4

USB is found in computers, tablets, mobiles, laptops, electronic equipment, modern gateways, servers and in many electronics devices. There are several versions of USB evolved over a period of time like all communication interfaces. Among them USB2.0 might be getting older now with USB3.0 coming up in the new electronic devices but it is most widely used communication interface in the embedded world. For the designer information, USB2.0 is called high speed USB and USB3.0 is called Super speed USB. USB2.0 operates around 480Mbps speed whereas USB3.0 operates at a maximum of 5Gbps speed. The following are the most important considerations for a layout engineer to consider before jumping into the layout activity.

1. Stack up -  with indication of USB signal routing layers
2. Impedance controlled routing
3. Trace width
4. Trace separation
5. Termination resistor placement
6. Trace length
7. Grounding considerations
8. Supply filtering
9. Other EMI/EMC considerations
10. USB controller placement
11. Layer splits and any voids

USB uses differential signaling for data transmission and all the above points are to be thoroughly listed for the routing and analyzed in depth before starting the routing. Whatever may be the routing techniques involved, maintaining the given signal quality is the ultimate goal. Let us look in this article the routing guidelines for the high speed USB.

1. Route the differential signals with as smaller lengths as possible.
2. Place the termination resistor as close as possible to the origin of USB signals.. In most cases, host is the originator, so, keep as close as possible to the host.
3. Proper length matching to be achieved with the USB signals. This meant two traces D+,D- should have same length. (mismatch must be < 150 mils)
4. Signals should have a continuous ground plane to maintain proper impedance, USB signals should always be routed as impedance controlled.
5. Never route the USB signals under clock generators, crystals, oscillators.
6. Ensure proper separation between USB differential signals during the break out or terminating to the connector. the spacing between the signals determine the impedance.
7. USB signals should not cross any power/ground splits. If they cross that enables the return path to take a longer route which is like increasing the ground loop causing necessary signal integrity issues.
8. Route the USB signals in a strip line topology. This meant that they must be routed in the inner layers to avoid any EMI issues in the system.
9. While routing in the inner layers, take care that there are minimum vias. As the number of vias increases, impedance mismatch occurs and hence reflections leading to signal degradation.
10. Avoid right angle bends at the corners, this causes reflections. Have a smoother routing with < 45 deg routing near the corners.
11. USB signals should have sufficient spacing from high speed clocks and periodic signals to avoid any signal coupling.
12. USB signals should not have any stubs. Stub at any point causes impedance discontinuity. Generally, for testing signals people tend to have a small stub with a test point. In such cases, don't have a stub more than 100 mils.
13. Route the signals away from the board edges to avoid unnecessary coupling with the loose cables surrounding the system.
14. Route signals with 90 ohms differential impedance as per USB standard.
15. Follow the trace width specified by your manufacturer for achieving the USB standard impedance.
16. Common mode choke must be placed as close as possible to the USB connector. Common mode chokes are used to filter common mode electromagnetic interference (EMI) currents without de-rating under high currents and without causing signal degradation.
17. Effects of Split plane crossing can minimized by having stitching capacitors near by. 

High speed Designs - Part 5

To eliminate Signal Integrity issues on the board,

1. Signals must be routed with good impedance control.

Impedance controlled routing is one of the important requirement in the high speed board designs. This involves routing done on the PCB with a single impedance across the board. The reason why impedance control is important is to eliminate the signal integrity issues because of different impedance values. The signals have different trace widths in different layers to achieve the same impedance for the signal in all layers. This need to be adhered to for reliable channel communication.

2. Follow proper design guidelines

Every component we have selected has a datasheet, design guidelines every engineer has to follow during their design. The component vendor would have done a thorough review/analysis before releasing their chip set/component. Follow the recommendations for a successful. Some times you might have to deviate from the guidelines, in such cases it always important to simulate the design before going ahead with the next steps.

3. Simulate the design

Simulation is the most important step in the design to evaluate the performance of the design before taking it to the fabrication. The simulation will be done before as well as after the layout. This helps us to predict and eliminate the signal integrity and power integrity issues that may come on the board. Hyper Lynx is the widely used tool in this scenario.

4. Routing to eliminate EMI/EMC issues

Certification is the most important step for the product. Certification is directly the product performance under various external conditions. In the first we have discussed about the impedance control in PCB routing, on the same lines, there are several other routing guidelines that need to be followed, like for example, routing most of the high frequency signals in in the inner layers with proper reference plane, proper power supply design architecture, careful component selection, eliminating leakages, proper shielding techniques, etc.

We will discuss on the other guidelines in the future articles.

PCB Routing guidelines - Part 3

Clock is the most important signal in any electronics design. This is the signal that helps the entire board to be in sync. Routing of clock is critical to the board performance and hence system functionality. There are several guidelines defined for the clock signal for best performance. The timing of the circuit depends on the clock signal. The rising/falling edge of the signal is critical as that helps to trigger the electronics circuit performance. It is rather important to take care of pulse edge than the entire pulse width.

Let us have a look at the guidelines for routing a single ended clock on a PCB:

1. The clock traces should be routed as straight as possible without any bends.

2. In case, bends can't be avoided, avoid right angle/sharp bends. 

3. Try to route the clock as arc at the bends.

Reason: Sharp bends causes reflections, affecting the integrity of the signal.

4. Never route the clock signals on the different layers. This will increase the number of vias. 

5. In the present day scenario of denser boards, clocks can't be routed in single layer. In such cases, take care that clock routing is done in not more than 2 layers.

Reason: vias result in impedance mismatch and causes reflections, affecting the integrity of the signal. Also low losses on the clock signal if lesser number of vias. increased delays because of vias.

6. When a top or bottom layer is used for clock routing, the immediate layer must be a ground. This improves the return path continuity and reduces EMI on the board.

7. When routed in the inner layers, the top and bottom layer of that inner layer must be ground. This eliminates any emissions.

8. Clocks must always be routed point-to-point. Any branches on clock signal will lead to catastrophic signal events.

9. It is always preferred to do pre and post layout analysis on the clock signal and apply proper termination.

10. If the clock is routed only on the top/bottom layer, try to have a guard trace around the clock. In case, space doesn't permit have enough spacing to clock from other signals. (Note: Maintain a spacing of 3X the width of the clock signal)

11. It is always preferred to route clock signal as short as possible.

12. Ensure proper return path for the clock signal to avoid longer return paths on the ground.

13.  If clock signal is routed in the inner layer, timing analysis is to be done. This is very essential for high frequency clocks.

14. Crystal and load capacitors should be as close as possible to the crystal Xin and Xout pins.

Clock signal routing is a trade-off. There will be a lot of debate whether to route on the top layer to avoid losses/reflections or to route in the inner layer to help emission on the board. but preferably, high speed clocks should always be routed in the inner layers.

High speed Designs - Part 4

One of the challenging aspects in the high speed board design is the selection of the PCB material. At low frequencies, the characteristics of the PCB material are of less significance as the signal characteristics doesn't change with type of material. But when it comes to high frequencies, dielectric material properties always a crucial role in the electrical performance. As most of us worked on low frequencies, the most available, cheap and widely used laminate material is FR4. The characteristics of FR4 does not allow it to be used for high frequencies. To decide on which material works best for a given frequency, we have to check out the specifications of the material datasheet as we do for the component selection. One more approach by the design engineers and fab houses is to use some simulation tool to decide the material characteristics to be used for a given scenario.

           The circuit designs range from low frequency digital and analog type to a high frequency digital and RF designs. As designers, we understand that characteristics of high speed digital and RF/microwave circuits differ a lot. So, in dielectric selection, considering the signal type is of primary importance and we understand that even in the high frequency domain, not all signal types will use the same laminate material. For a high frequency digital signal, the tolerance is more than the RF/Microwave. So, component selection for  RF/Microwave is more critical.

               As designers, we have to understand that quality should be the prime motto and the timeline for the project delivery must follow it. As a quality check, thorough analysis of application vs dielectric type to be used is a must and some significant amount of time must be spent on this. 

What are the material characteristics that need to be considered for selecting a laminate material?

1. Dielectric constant
2. Dielectric thickness
3. Loss tangent
4. Impedance characteristic
5. Temperature curve
6. Cost

Effects of  improper dielectric material selection:

1.  Impedance mismatch and hence reflection
2. Dielectric loss (signal loss in the material) - Skin effect

Impedance of the material seen by the signal varies as per the signal frequency. Also, with temperature the impedance varies. Another major factor is the process variation by different fab vendors resulting in minute variations which can create signal losses post fabrication.

The below are the dielectric materials preferred for high frequency applications:

1. Nelco 4000 
2. Rogers 4350

The below figure describes the core and pre-peg terminologies in a stack up.

PCB Routing guidelines - Part 2

Difference between Power Plane and Power Bus:

Layout engineers face different challenges in the real world. One of the biggest challenge is routing the power lines. A board with bigger stack up (meant more layers) will have a chance for separate power plane. Anyways with the present day board densities, and push for low cost designs, push for lesser number of layers is always on the cards. It is always a wise decision by the product management team to give the required freedom to the layout engineer as he is also a critical stakeholder for the product.

           Designs will always have more than one power rail to be routed on the board. PCB layout doesn't have enough space to have a single layer for each power rail. so, in the stack up power plane will be defined in one of the layer with a return path as ground in the next layer. The power plane will be split to accommodate the different power rails. It is the design strategy that need to be planned by the PCB layout engineer to have enough plane for each power rail to accommodate the current requirement. 

              Most of the times we have been talking about the space to route power rail on a separate plane. But this is not the case in smaller designs like for example, a 2-layer, 4-layer and sometimes 6-layer board. In this case, power rails can't have a separate plane but they have to routed as thicker traces to allow sufficient current to flow. 

The main disadvantage with power bus routing can be explained by a simple example:

Let us assume that a 5V rail is routed as power bus from the source to 3 chipsets. The following are the parameters defined in this scenario:

Voltage rail = 5V

Power Bus resistance = 200mohm (mainly because of trace width)

Each chip requires current = 1.5A, so, a total of 1.5*3 = 4.5A

So, 4.5A should flow through the power bus of 200mohm

Drop across power bus = 200mohm * 4.5 = 0.9V

That means, in power bus routing with above example, the 3rd device in the chain will only see 5-0.9 = 4.1V, which may not be sufficient excitation in most of the times.

As per the design rule, as trace width increases, impedance reduces. As impedance reduces, the drop reduces. This meant for power rails, we must have a wider plane to eliminate any drop due to trace routing. This is a clear indication that it is always safer to have power plane rather than having power bus and then distributing power to various devices on the board.

Understanding Boost Regulator

As the name suggests, Boost Regulator is a power supply component that boosts the input voltage to a desired value. Let us take a alkaline battery which gives a voltage of 1.5V.  In case, the circuit has to be operated at 3.3V, we have to use a boost converter in between to boost to a desired voltage of 3.3V. The basic boost converter circuit principle is based on the following circuit:

As shown in the above basic circuit of Boost converter, the main component in the Boost circuit are Inductor, Switch and a diode. The switch must be a low resistance semi-conductor device like a MOSFET.

Operation of the above circuit:

1. When the switch 'S' is closed, the current passes through the inductor through the switch 'S'. The inductor charges with + at the source side and - at the switch side. The inductor generates a magnetic field around it.
2. Once the switch is open, no current passes though switch 'S'. The charged inductor slowly discharges and the current now passes through the Diode 'D' to the load. The resultant current to the load increases as the source will be adding to the inductor current.
3. By the time inductor fully discharges, if the switch is closed, the inductor charges again. As the inductor is not allowed to discharge fully, the voltage across the load seen is sum of source voltage and inductor voltage. This meant that the output voltage is always greater than the source voltage.
4. The capacitor 'C' supplies to the load when the switch is closed. the diode in this case acts as blocking diode not allowing any current from capacitor pass through to the switch side.
5. So, when switch is closed, capacitor supplies to the load and when the switch is open, source+inductor supplies to the load and also charges the capacitor.
6. Input filter requirements are little relaxed as the supply sees a constant inductor load and there isn't discontinuous currents and need for filtering.

The diode used in this circuit is called "fly-back" diode. The fly-back diode is sometimes replaced by another low-resistance switch in low power applications. This is to avoid the diode losses.

The following parameters are to be checked while selecting a Boost converter:

1. Input voltage range
2. Output voltage (fixed/adjustable)
3. Output current
4. Switching frequency
5. Efficiency
6. Maximum switch current
7. Mosfet internal resistance
8. Quiescent current

All the above parameters are available from the datasheet of the boost converter ic.

Some of the important points of boost converter:

1. As the input voltage is reduced for a given fixed output voltage, the current drawn by the switch of the Boost converter increases, in this case the efficiency of the boost converter is less. The below figure from the data sheet of boost converter IC LM2621 illustrates the same:

2. At low load current conditions, the ripple current causes the inductor to discharge more quickly. This is the condition during which the modern step-up converters manage by varying the switching frequency.

Analog Circuits - PCB surface leakage current

The latest opamps in the market have good offset performance and very low bias currents. The bias current will be of the order of the 1pA and even of the order of fA. Take for example the latest precision opamp LMP7721 from Texas Instruments which has input bias current as low as 3fA. This is very low and requires very good layout design to take advantage of the good offset and drift performance.

                Leakage effect is one of the primary concerns in such circuits. The leakage can be through the PCB crosstalk which can easily draw more current than the input current drawn by the opamp pins. This is more prevalent in the high temperature and high voltage applications. Over a period of time the dust, humidity and other impurities formed over the PCB aggravates the problem and should be taken care with good layout practices. The impurities that we are talking here can be a flux residue which is left over due to improper PCB cleaning techniques. So, the following procedures are must in such critical applications:

1.       Surface coating on the PCB to avoid humidity, dust accumulation

2.       Using high quality dielectric materials

3.       Proper PCB cleaning techniques

4.       Good layout techniques

Example scenario:

Take for example a PCB trace whose impedance w.r.t given trace nearby is 110K and a 3.3V is applied across the main trace. In this case the current passing across that junction would be 30uA. If the input bias current of an opamp is comparable with this current, then definitely the circuit will misbehave. In such cases we have implement the following technique to avoid that leakage:

Have a guard trace around the trace carrying low current. This guard trace must have a potential very close to main trace. The below snapshot shows guard ring recommendation for the LMC6001 Ultra, Ultra-Low Input Current Amplifier.