Clock is the most important signal in any electronics design. This is the signal that helps the entire board to be in sync. Routing of clock is critical to the board performance and hence system functionality. There are several guidelines defined for the clock signal for best performance. The timing of the circuit depends on the clock signal. The rising/falling edge of the signal is critical as that helps to trigger the electronics circuit performance. It is rather important to take care of pulse edge than the entire pulse width.
Let us have a look at the guidelines for routing a single ended clock on a PCB:
1. The clock traces should be routed as straight as possible without any bends.
2. In case, bends can't be avoided, avoid right angle/sharp bends.
3. Try to route the clock as arc at the bends.
Reason: Sharp bends causes reflections, affecting the integrity of the signal.
4. Never route the clock signals on the different layers. This will increase the number of vias.
5. In the present day scenario of denser boards, clocks can't be routed in single layer. In such cases, take care that clock routing is done in not more than 2 layers.
Reason: vias result in impedance mismatch and causes reflections, affecting the integrity of the signal. Also low losses on the clock signal if lesser number of vias. increased delays because of vias.
6. When a top or bottom layer is used for clock routing, the immediate layer must be a ground. This improves the return path continuity and reduces EMI on the board.
7. When routed in the inner layers, the top and bottom layer of that inner layer must be ground. This eliminates any emissions.
8. Clocks must always be routed point-to-point. Any branches on clock signal will lead to catastrophic signal events.
9. It is always preferred to do pre and post layout analysis on the clock signal and apply proper termination.
10. If the clock is routed only on the top/bottom layer, try to have a guard trace around the clock. In case, space doesn't permit have enough spacing to clock from other signals. (Note: Maintain a spacing of 3X the width of the clock signal)
11. It is always preferred to route clock signal as short as possible.
12. Ensure proper return path for the clock signal to avoid longer return paths on the ground.
13. If clock signal is routed in the inner layer, timing analysis is to be done. This is very essential for high frequency clocks.
14. Crystal and load capacitors should be as close as possible to the crystal Xin and Xout pins.
Clock signal routing is a trade-off. There will be a lot of debate whether to route on the top layer to avoid losses/reflections or to route in the inner layer to help emission on the board. but preferably, high speed clocks should always be routed in the inner layers.
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